1. Field of the Invention
The present invention relates generally to electrostatic discharge (ESD) protection of integrated circuits. More particularly, the invention relates to ESD protection of high voltage power (&gt;b 25 V) input terminals, and especially for applications where power devices are used in conjunction with printing elements to form a customer replacable unit such as a printhead or print cartridge which will be handled in a wide variety of environments that are hostile to semiconductor components.
2. Description of Related Art
Semiconductor devices have become increasingly susceptible to damage by ESD events as the scale of the devices has decreased. The increased static sensitivity has been addressed by on chip protection circuits which protect inputs to about 2 to 4 kV [as measured by the Human Body Model (HBM)] in conjunction with stringent circuit handling precautions. In a consumer environment, such as an office, ESD events of up to 10 KV (HBM) are not uncommon. Such high-level ESD events are easily sufficient to destroy normal circuit components. In electronic devices, such as thermal ink jet printers or the like, which are designed to have easily replaceable electronic modules for on-site repair, high ESD hardness is necessary in order to prevent the replacement modules from being damaged as (or even before) they are installed in the electronic device. Previous inventions, for example U.S. Pat. Nos. 4,947,192 and 5,075,250 to Hawkins and Burke and to the same asignee as this application, disclose methods for integrating printing elements with control logic and power transistors switches. Integration of control logic dramatically reduces the number of connections which need to be made to the printhead, but adds the requirement of robust static protection.
Numerous conventional systems are known for ESD protection of semiconductor and MOS devices. The inputs of MOS integrated circuits are capacitors whose two electrodes are the MOS transistor device channel and the gate electrode material, usually polysilicon. The two capacitor electrodes are separated by silicon dioxide, which is usually grown on the device channel by high temperature oxidation processes. The MOS transistors use a thin silicon dioxide gate insulator to achieve high performance, and this thin oxide is susceptable to catastrophic, irreversable breakdown if the voltage across the dielectric is raised above 20 to 100 volts, depending on device fabrication details. In general, such circuits use monolithically integrated protective transistors built into the semiconductor circuit to protect the gates of the devices. These protective transistors are arranged to allow a high voltage static discharge transient to pass to ground prior to reaching the protected circuit. For example, U.S. Pat. No. 4,990,984 to Misu discloses a conventional protective transistor ESD protection device for an integrated circuit.
Such systems have at least three disadvantages which prevent them from being applied as protection of high voltage power input terminals. First, the conventional protective transistor for the circuit has only a small current carrying capacity, so that ESD surges which are encountered in the office environment will overwhelm the protective transistor, allowing a part of the ESD surge to reach the protected circuit or causing failure of the ESD protection circuit itself. Second, conventional protective transistors are designed to protect logic input terminals, which have a low current signal input voltage of 5 V. Accordingly, these protective transistors are designed to break down at 15 to 25 V. Advanced VLSI technologies utilize reduced gate dielectric thickness and CMOS fabrication, so the industry trend is to reduce the voltage at which ESD input protection structures breakdown, since the gate dielectric becomes more susceptable to breakdown as it becomes thinner. Such conventional ESD protective circuits are worthless when attempting to protect high voltage (&gt;25 V) input terminals. Finally, protection circuits for logic input gates use diffused resistors which have values of several hundred ohms to slow ESD current transients. Such high impedence is not useful for power input pad applications.
In U.S. Pat. Nos. 5,027,252 to Yamamura and 4,616,243 to Minato et al., the first disadvantage of the conventional ESD protective transistors for semiconductor circuit gates is addressed by providing a multiple stage protective circuit. Yamamura teaches use of a three stage protection circuit, as shown in their FIG. 6 and 7. The first stage is a punch through device under field oxide, and is connected directly to the input pad. The second stage is isolated from the first stage by a current limiting diffused resistor and is a thick oxide device with it's gate tied to the input pad. The diffused resistor is situated between the gate connection and the drain, and the device source is tied to ground. A second diffused resistor is then followed by the third stage, where a conventional n-channel device with it's gate and source tied to ground is used to discharge any remaining voltage to ground. Minato teaches techniques for protecting p-well CMOS logic inputs. A polysilicon current limiting resistor is connected to the input pad and is followed by an n-channel device which is placed in a p-well that is specifically tailored to breakdown before normal p-well transistors. The breakdown voltage is lowered by raising the doping level of the protective transistor p-well, diffusing the p-well to a shallower depth, or adding diffused features which reduce p-well breakdown by other methods.
However, use of a punch-through type protection transistor with a high voltage input terminal for a MOS power driver is not practical for several reasons. First, the approach is limited to CMOS-type circuitry, while power MOS devices may employ either CMOS or NMOS architecture and circuitry. Secondly, all the proposed input circuits utilize diffused or polysilicon resistors with substantial attendent input impedence, and which would therefore seriously limit the ability of the input connection to supply a tightly regulated voltage over the range of current flows typically required for power applications. Finally, these input protection circuits breakdown at voltages which are far below that required for the present applications, as is shown in FIG. 4 of U.S. Pat. No. 4,616,243, where breakdown occurs between 10 and 15 Volts.
U.S. Pat. No. 4,725,915 to Jwahashi discloses a protection circuit for protecting the drain of a CMOS circuit having a higher voltage (&gt;5 V, but &lt;25 V) input terminal, by providing a higher breakdown voltage (.about.26 V) transistor and a resistor in parallel with the drain of a transistor of the protected circuit. In this case, the circuit to be protected is used for writing of EPROM's, where there is a high writing voltage applied. The drain of the transistor connected to the write voltage is an offset gate device with a drift region 4 between the gate 6 and the diffusion 2, as shown in their FIG. 2. The protection transistor has a lower breakdown voltage than the protected offset gate circuit because a thicker gate insulation layer 13 is combined together with abutting diffusion 12 directly against the gate electrode 14, as seen in their FIG. 4, while the gate insulation layer provided on the transistors in the protected circuits is substantially thinner but the diffusion is offset from the gate electrode by a drift region. The resistor is connected in series with the protective transistor in a common gate-source configuration and to ground. However, as shown in FIG. 5 of Jwahashi, the protection circuit can withstand ESD voltages up to only about 450 V before the protected circuit is damaged, and such a modest level of protection still requires 50 ohms of resistance.